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| Preliminary K1S16161CA Document Title 1Mx16 bit Page Mode Uni-Transistor Random Access Memory UtRAM Revision History Revision No. History 0.0 Initial Draft Draft Date Remark December 12, 2003 Preliminary The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. -1- Revision 0.0 December 2003 Preliminary K1S16161CA 1M x 16 bit Page Mode Uni-Transistor CMOS RAM FEATURES * * * * * UtRAM GENERAL DESCRIPTION The K1S16161CA is fabricated by SAMSUNGs advanced CMOS technology using one transistor memory cell. The device support 4 page mode operation, Industrial temperature range and 48 ball Chip Scale Package for user flexibility of system design. The device also supports deep power down mode for low standby current. Process Technology: CMOS Organization: 1M x16 bit Power Supply Voltage: 2.7~3.1V Three State Outputs Compatible with Low Power SRAM * Support 4 page read mode * Package Type: 48-FBGA-6.00x7.00 PRODUCT FAMILY Product Family Operating Temp. Vcc Range Speed (tRC) 70ns Power Dissipation Standby (ISB1, Max.) 80A Operating (ICC2, Max.) 35mA PKG Type K1S16161CA-I Industrial(-40~85C) 2.7~3.1V 48-FBGA-6.00x7.00 PIN DESCRIPTION 1 2 3 4 5 6 FUNCTIONAL BLOCK DIAGRAM Clk gen. Precharge circuit. A LB OE A0 A1 A2 CS2 Vcc Vss B I/O9 UB A3 A4 CS1 I/O1 Row Addresses Row select Memory array C I/O10 I/O11 A5 A6 I/O2 I/O3 D Vss I/O12 A17 A7 I/O4 Vcc I/O1~I/O8 E Vcc I/O13 NC A16 I/O5 Vss I/O9~I/O16 Data cont Data cont Data cont I/O Circuit Column select F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 A19 A12 A13 WE I/O8 Column Addresses H A18 A8 A9 A10 A11 NC CS1 CS2 OE WE UB 48-FBGA: Top View(Ball Down) Control Logic Name Function Name Vcc Vss UB LB NC Function Power Ground Upper Byte(I/O9~16) Lower Byte(I/O1~8) No Connection1) LB CS1,CS2 Chip Select Inputs OE WE A0~A19 Output Enable Input Write Enable Input Address Inputs I/O1~I/O16 Data Inputs/Outputs 1) Reserved for future use SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. -2Revision 0.0 December 2003 Preliminary K1S16161CA POWER UP SEQUENCE 1. Apply power. 2. Maintain stable power(Vcc min.=2.7V) for a minimum 200s with CS1=high.or CS2=low. UtRAM TIMING WAVEFORM OF POWER UP(1) (CS1 controlled) VCC(Min) VCC Min. 200s CS1 CS2 Power Up Mode POWER UP(1) Normal Operation 1. After VCC reaches VCC(Min.), wait 200s with CS1 high. Then the device gets into the normal operation. TIMING WAVEFORM OF POWER UP(2) (CS2 controlled) VCC(Min) VCC Min. 200s CS1 CS2 Power Up Mode Normal Operation POWER UP(2) 1. After VCC reaches VCC(Min.), wait 200s with CS2 low. Then the device gets into the normal operation. -3- Revision 0.0 December 2003 Preliminary K1S16161CA FUNCTIONAL DESCRIPTION CS1 H X1) X1) L L L L L L L L CS2 X 1) UtRAM OE X 1) WE X 1) LB X 1) UB X 1) I/O1~8 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din I/O9~16 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Standby Standby Standby Active Active Active Active Active Active Active Active L X1) H H H H H H H H X1) X1) H H L L L X X 1) 1) X1) X1) H H H H H L L L X1) H L X 1) X1) H X1) L H L L H L L L H L L H L X1) 1. X means dont care.(Must be low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN, VOUT VCC PD TSTG TA Ratings -0.2 to VCC+0.3V -0.2 to 3.6V 1.0 -65 to 150 -40 to 85 Unit V V W C C 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability. -4- Revision 0.0 December 2003 Preliminary K1S16161CA PRODUCT LIST Industrial Temperature Product(-40~85C) Part Name K1S16161CA-FI70 K1S16161CA-BI701) 1. Lead Free Product UtRAM Function 48-FBGA, 70ns, 2.9V 48-FBGA, 70ns, 2.9V RECOMMENDED DC OPERATING CONDITIONS1) Item Supply voltage Ground Input high voltage Input low voltage 1. TA=-40 to 85C, otherwise specified. 2. Overshoot: Vcc+1.0V in case of pulse width 20ns. 3. Undershoot: -1.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested. Symbol Vcc Vss VIH VIL Min 2.7 0 2.2 -0.2 3) Typ 2.9 0 - Max 3.1 0 Vcc+0.32) 0.6 Unit V V V V CAPACITANCE1)(f=1MHz, TA=25C) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested. Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 10 Unit pF pF DC AND OPERATING CHARACTERISTICS Item Input leakage current Output leakage current Symbol Test Conditions VIN=Vss to Vcc CS=VIH, ZZ=VIH, OE=VIH or WE=VIL, VIO=Vss to Vcc Cycle time=1s, 100% duty, IIO=0mA, CS0.2V, ZZVcc-0.2V, VIN0.2V or VINVCC-0.2V Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS=VIL, ZZ=VIH, VIN=VIL or VIH IOL=2.1mA IOH=-1.0mA CSVcc-0.2V, ZZVcc-0.2V, Other inputs=Vss to Vcc Min -1 -1 2.4 - Typ1) - Max 1 1 7 35 Unit A A mA mA V V A ILI ILO ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current(CMOS) VOL VOH ISB12) - 0.4 80 1. Typical values are tested at VCC=2.9V, TA=25C and not guaranteed. -5- Revision 0.0 December 2003 Preliminary K1S16161CA AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Test Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load: CL=50pF CL 1. Including scope and jig capacitance UtRAM Dout AC CHARACTERISTICS(Vcc=2.7~3.1V, TA=-40 to 85C) Speed Bin Parameter List Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output UB, LB Access Time Chip Select to Low-Z Output Read UB, LB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB, LB Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Page Cycle Page Access Time Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write UB, LB Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z 1. tWP(min) =70ns for continuous write operation over 50 times. 70ns1) Max 70 70 35 70 25 25 25 20 25 - Units tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tPC tPA tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW 70 10 10 5 0 0 0 5 25 70 60 0 60 60 551) 0 0 30 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -6- Revision 0.0 December 2003 Preliminary K1S16161CA TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1)(Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL) tRC Address tOH Data Out Previous Data Valid tAA Data Valid UtRAM TIMING WAVEFORM OF READ CYCLE(2)(WE=VIH) tRC Address tAA CS1 tCO tOH CS2 tHZ tBA UB, LB tBHZ tOE OE tOLZ tBLZ tLZ Data Valid tOHZ Data out High-Z TIMING WAVEFORM OF PAGE CYCLE(READ ONLY) A20~A2 Valid Address A1~A0 Valid Address Valid Address Valid Address Valid Address tAA CS1 tPC CS2 tCO OE tOE DQ15~DQ0 (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. tOE(max) is met only when OE becomes enabled after tAA(max). 4. If invalid address signals shorter than min. tRC are continuously repeated for over 4us, the device needs a normal read timing(tRC) or needs to sustain standby state for min. tRC at least once in every 4us. tPA Data Valid Data Valid Data Valid Data Valid tOHZ High Z -7- Revision 0.0 December 2003 Preliminary K1S16161CA TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW CS1 tWR UtRAM CS2 tAW tBW tWP WE tAS Data in High-Z tWHZ Data out Data Undefined tDW Data Valid tOW tDH High-Z UB, LB TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tAS CS1 tAW CS2 tBW UB, LB tWP WE tDW Data in Data Valid tDH tCW tWR Data out High-Z -8- Revision 0.0 December 2003 Preliminary K1S16161CA TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled) tWC Address tAS CS1 tAW CS2 tBW UB, LB tWP(1) WE tDW Data in Data Valid tDH tCW tWR UtRAM Data out High-Z TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled) tWC Address tCW CS1 tAW CS2 UB, LB tAS WE tDW Data in Data Valid tDH tBW tWP tWR Data out NOTES (WRITE CYCLE) High-Z 1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1 going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high. -9- Revision 0.0 December 2003 Preliminary K1S16161CA PACKAGE DIMENSION 48 BALL FINE PITCH BGA(0.75mm ball pitch) Top View Bottom View B B 6 A #A1 B C D C1 E C1/2 F G H B/2 Detail A A 0.35/Typ. Y 0.55/Typ. Notes. 1. Bump counts: 48(8 row x 6 column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerence are 0.050 unless specified beside figures. 4. Typ : Typical 5. Y is coplanarity: 0.10(Max) - 10 C 5 4 B1 UtRAM Unit: millimeters 3 2 1 Side View D C Min A B B1 C C1 D E E1 E2 Y 5.90 7.90 0.40 0.30 - Typ 0.75 6.00 3.75 8.00 5.25 0.45 0.90 0.55 0.35 - Max 6.10 8.10 0.50 1.00 0.40 0.10 Revision 0.0 December 2003 C E2 E1 E |
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